The present invention relates generally to integrated circuits, and in particular to delay locked loop.
Delay locked loops (DLL) are often used in integrated circuits (ICs) to generate an internal clock signal from an external clock signal. The internal clock signal usually as the same frequency or clock cycle as the external clock signal. However, the internal clock signal is used in place of the external clock signal to control certain operation within the IC because it is more manageable. It is also more accurate and matches the operating condition of the IC better than the external clock signal.
Since it is generated from the external clock signal, the internal clock signal is preferred to be synchronized with the external clock signal. To synchronize the two clock signals, a phase detector of the DLL compares a phase difference between them and applies an appropriate amount of delay until the internal clock signal is synchronized with the external clock signal. When the external and internal clock signals are synchronized, the DLL is locked.
In some instances, the DLL needs to be reset. For example, the DLL needs to be reset to start a new operation within the IC. In some of these instances, the reset can put the DLL in a false lock. A false lock occurs during the reset because the DLL might have compared the previously synchronized external and internal signals from before the reset, instead of comparing the external signal and the internal clock signal generated after the reset; because the internal clock signal generated after the reset may not arrive at the phase detector of the DLL on time for the comparison.
Thus, there is a need for a scheme to protect the DLL from a false lock during a reset.
The present invention includes a novel DLL having a false lock protection circuit. The false lock protection circuit prevents the DLL from performing a false lock during a reset of the DLL.
In one aspect, a method of operating a DLL is provided. The method includes activating a reset mode signal to prevent a phase lock signal from forcing the DLL out of a reset. The method also includes deactivating the reset mode signal only after at least one shifting operation is performed to allow the phase lock signal to correctly take the DLL out of the reset.
In another aspect, a delay locked loop (DLL) is provided. The DLL includes a delay line to receive an external signal to generate an internal signal. The DLL also includes a phase detector for comparing the external signal and a delayed version of the internal signal. The phase detector produces a phase lock signal when the external and internal signals are synchronized. The DLL further includes a false lock protection circuit for receiving the phase lock signal. The false lock protection circuit blocks the phase lock signal from forcing the DLL out of a reset when the external signal and an internal signal generated after receiving the reset signal are not synchronized.
FIG. 1 is an integrated circuit having a DLL according to one embodiment of the invention.
FIG. 2 is a block diagram of a phase detector of the DLL of FIG. 1.
FIG. 3 is a schematic diagram of a false lock protection circuit of the phase detector of FIG. 2.
FIG. 4 is a timing diagram illustrating the operation of the false lock protection circuit of FIG. 3.
FIG. 5 is a block diagram of a memory device having the DLL according to another embodiment of the invention.
FIG. 6 is a block diagram of a system according to another embodiment of the invention.